1. Field of the Invention
The present invention relates generally to an A/D converter and more particularly, to an improvement of an A/D converter of a flash type.
2. Description of the Prior Art
A so-called A/D converter of a flash type has been used in the field of picture processing or the like because it can process at high speed. FIG. 1 is a circuit diagram showing an example of a conventional A/D converter of a flash type, which is described in, for example, an article by Andrew G. F. Dingwall, entitled "Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, No. 6, DECEMBER, 1979, pp. 926-932. Referring to FIG. 1, reference voltages VR.sup.+ and VR.sup.- are applied to reference voltage terminals 3 and 4, respectively. A voltage between the reference voltages VR.sup.+ and VR.sup.- is divided by connecting 128 resistors 6 in series between the reference voltage terminals 3 and 4. Assuming that the reference numbers of 0 to 127 are given to the 128 resistors 6 in the order from the reference voltage VR.sup.- side to the reference voltage VR.sup.+ side, a potential VR(m) of a node N(m) in one end of the m-th resistor is represented by the following equation: EQU VR(m)=(m/128).multidot.(VR.sup.+ -VR.sup.-)+VR.sup.- ( 1)
Each of the 127 voltages obtained by division by the resistors is applied to a minus terminal of each of 127 comparators 7. An analogue input voltage Vin is applied from an analogue signal input terminal 1 to positive terminals of all of the comparators 7.
It is assumed that the logical value of an output of the comparator 7 to which the potential VR(m) is inputted is C(m). Assuming that the analogue signal Vin which satisfies the following relation is inputted; EQU VR(m)&lt;Vin&lt;VR(m+1) (2)
an output C(k) of the k-th comparator is as follows: ##EQU1##
Outputs of the comparators 7 are latched in D type flip-flops 8 in synchronization with a sampling clock pulse .phi. inputted from a clock terminal 2. Assuming that an output of the D type flip-flop 8 to which the output C(m) is inputted is E(m), an AND gate 9 performs the following operation; EQU F(m)=E(m).andgate.E(m+1) (4)
where F(mA) is an output value of the AND gate 9. An output F(k) of the k-th AND gate 9 is as follows: ##EQU2## In summary, only F(m) is "1" and the others are "0" with respect to an input which satisfies the following relation: EQU VR(m)&lt;Vin&lt;VR(m+1) (6)
An encoder 10 comprises an ROM or the like, and provides outputs b0 to b7 shown in FIG. 2 with respect to addresses 0 to 127. More specifically, a binary m is outputted with respect to an address m. The output b0 to b7 are latched in D type flip-flops 11 in synchronization with an inverted sampling clock pulse .phi. outputted from an inverter 12. The D type flip-flops 11 output digital signals D0 to D7.
In the above described manner, the conventional A/D converter of a flash type converts an analogue value to a digital value.
The above described A/D converter of a flash type requires at least the following value as the absolute value of resolution of the comparators 7: EQU (VR.sup.+ -VR.sup.-)/128 (7)
For example, assuming that VR.sup.+ -VR.sup.- =3 V, required resolution is approximately 23 mV. Technically it is very difficult to achieve such resolution. It is difficult particularly if an MOS transistor is used, because the threshold value significantly changes in the process. Thus, the resolution of the comparators 7 may not be satisfied due to the problems caused by the design and the process. In such a case, even if a signal as represented by the above described equation (2) is inputted, C(k) (k=0, 1, . . . , 127) does not necessarily satisfy the relation as represented by the above described equation (3).
For example, it is assumed that a signal which satisfies the following relation is inputted: EQU VR(62)&lt;Vin&lt;VR(63) (8)
It is assumed that the resolution of the comparators 7 does not satisfy the above described equation (7), a comparator which outputs, for example, C(61) and C(62) tends to output "0" and a comparator which outputs, for example, C(63) and C(64) tends to output "1". Such a state may occur near a folded point of patterning, for example, when the comparators 7 are formed on a semiconductor substrate. Therefore, it is assumed that the comparators 7 provide outputs which satisfy the following relations, as shown in FIG. 3: ##EQU3## In this case, if the comparators 7 essentially have required resolution, the following relations should be satisfied: ##EQU4## However, since the resolution is bad, C(61), . . . , C(64) are erroneous outputs.
By the outputs of the comparators 7, outputs of the AND gates 9, that is, inputs to the encoder 10 are as follows: ##EQU5##
The encoder 10 generally comprises a ROM. When a plurality of addresses are selected as represented by the above described equation (11), the OR or the AND for every bit of outputs corresponding to the addresses is outputted. FIG. 4 is a circuit diagram showing a part of an encoder from which the OR is outputted. In the above described example, addresses "60" and "64" of the encoder 10 are selected, "60", i.e., "00111100" and "64", i.e., "01000000" are ORed for every bit, so that an output of the encoder 10 becomes "01111100", i.e., "124".
As described in the foregoing, if resolution of the comparators 7 is insufficient, "124" may be erroneously outputted even if there exists an analogue input which should correctly output a code "63".
The cause of the above described error is that a plurality of addresses instead of one only in the encoder 10 are selected. In the above described example, the difference between a digital output and the correct value thereof is 61, so that a fatal error is caused.